1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for processing instructions of a computer program and for comparing register identifiers and attribute data associated with the instructions to detect data hazards between the instructions.
2. Related Art
To increase the performance of many processors, pipeline processing has been developed. In pipeline processing, a processor is equipped with at least one pipeline that can simultaneously process multiple instructions. Therefore, execution of one instruction in the pipeline may be commenced before the results of execution of a preceding instruction in the pipeline are available, and as a result, errors from data dependency hazards are possible.
A data dependency exists when one instruction to be executed by a pipeline utilizes data produced via execution of another instruction, and the data dependency creates a data dependency hazard when the data produced by the other instruction is not yet available for use by the one instruction. For example, a later instruction, when executed, may utilize data that is produced by execution of an earlier instruction (e.g., a later add instruction may utilize data that is retrieved by an earlier load instruction). If the later instruction executes before the data from execution of the earlier instruction is available, then the later instruction utilizes incorrect data, resulting in a data dependency error. Accordingly, a data dependency hazard exists between the two instructions, until the data utilized by the later instruction is available or until the data dependency error occurs.
Needless to say, it is important to detect data dependency hazards so that data dependency errors can be prevented. However, circuitry for detecting data dependency hazards is often complex and often utilizes a relatively large amount of area within a processor. This is especially true in superscalar processors, which include a plurality of pipelines that simultaneously execute instructions. In this regard, an instruction in one pipeline may not only have a dependency with another instruction in the same pipeline but may also have a dependency with another instruction in another pipeline. Therefore, to adequately check for data dependency hazards, a first instruction in one pipeline should be compared with each instruction in each pipeline that could share a data dependency hazard with the first instruction. Consequently, as the number of pipelines within a processor increases, the circuitry and complexity required to detect data dependencies that define data dependency hazards increase dramatically.
Furthermore, when a data dependency hazard is detected, an instruction associated with the data dependency hazard is often stalled to prevent errors, until the data dependency hazard expires. When an instruction is stalled, the processing of the instruction is temporarily halted. Since stalls generally increase the amount of time required to process instructions, it is desirable to limit the occurrence and duration of stalls whenever possible.
Thus, a heretofore unaddressed need exists in the industry for an efficient processing system with minimal complexity and circuitry for detecting data hazards between instructions of a computer program.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a system and method for processing instructions of a computer program and for detecting data hazards between the instructions.
In architecture, the system of the present invention utilizes at least one pipeline, a first decoder, a second decoder, and comparison logic. The pipeline receives and simultaneously processes instructions of a computer program. The first and second decoders are coupled to the pipeline and decode register identifiers associated with instructions being processed by the pipeline. The comparison logic is interfaced with the first and second decoders and receives the decoded register identifiers along with attribute data indicating the status and/or type of instructions being processed by the pipeline. The comparison logic compares the decoded register identifiers and the attribute data to other decoded register identifiers and attribute data associated with other instructions to detect data hazards.
In accordance with another feature of the present invention, an attribute interface receives a decoded register identifier and attribute data and combines the attribute data with the decoded register identifier.
The present invention can also be viewed as providing a method for processing instructions of a computer program. The method can be broadly conceptualized by the following steps: transmitting an instruction to a pipeline of a processing system; decoding an encoded register identifier associated with the instruction into a first decoded register identifier while the instruction is being processed by a first portion of the pipeline; decoding the encoded register identifier into a second decoded register identifier while the instruction is being processed by a second portion of the pipeline; transmitting a first set of attribute data associated with the instruction; transmitting a second set of attribute data associated with the instruction; comparing the first decoded register identifier and the first set of attribute data to decoded register identifiers and attribute data associated with other instructions; comparing the second decoded register identifier and the second set of attribute data to decoded register identifiers and attribute data associated with other instructions; and detecting data dependency hazards based on the comparing steps.